In modern microprocessor systems, processor cycle time continues to decrease as technology continues to improve. Also, design techniques of speculative execution, deeper pipelines, more execution elements and the like, continue to improve the performance of processing systems. The improved performance puts a heavier burden on the memory interface since the processor demands data and instructions more rapidly from memory. To increase the performance of processing systems, cache memory systems are often implemented.
Processing systems employing cache memories are well known in the art. Cache memories are very high-speed memory devices that increase the speed of a data processing system by making current programs and data available to a processor ("CPU") with a minimal amount of latency. Large on-chip caches (L1 caches) are implemented to help reduce the memory latency, and they are often augmented by larger off-chip caches (L2 caches).
The primary advantage behind cache memory systems is that by keeping the most frequently accessed instructions and data in the fast cache memory, the average memory access time of the overall processing system will approach the access time of the cache. Although cache memory is only a small fraction of the size of main memory, a large fraction of memory requests are successfully found in the fast cache memory because of the "locality of reference" property of programs. This property holds that memory references during any given time interval tend to be confined to a few localized areas of memory.
The basic operation of cache memories is well-known. When the CPU needs to access memory, the cache is examined. If the word addressed by the CPU is found in the cache, it is read from the fast memory. If the word addressed by the CPU is not found in the cache, the main memory is accessed to read the word. A block of words containing the word being accessed is then transferred from main memory to cache memory. In this manner, additional data is transferred to cache (pre-fetched) so that future references to memory will likely find the required words in the fast cache memory.
The average memory access time of the computer system can be improved considerably by use of a cache. The performance of cache memory is frequently measured in terms of a quantity called "hit ratio." When the CPU accesses memory and finds the word in cache, a cache "hit" results. If the word is found not in cache memory but in main memory, a cache "miss" results. If the CPU finds the word in cache most of the time, instead of main memory, a high hit ratio results and the average access time is close to the access time of the fast cache memory.
Pre-fetching techniques are often implemented to try to supply memory data to the on-chip L1 cache ahead of time to reduce latency. Ideally, data and instructions are pre-fetched far enough in advance so that a copy of the instructions and data is always in the L1 cache when the processor needs it. Pre-fetching of instructions and/or data is well-known in the art.
However, existing pre-fetching techniques often pre-fetch instructions and/or data prematurely. Data may be pre-fetched from a speculative data path and then may never be used when the processor executes a different data path. The unused data may also displace data needed by the processor, resulting in a redundant re-fetching of the needed data. The pre-fetch memory accesses often delay subsequent processor cache reloads of needed data, thus increasing the latency of the needed data. All of these effects lower the efficiency of the CPU. These problems stem chiefly from the fact that "mainline" cache misses are treated the same as speculative pre-fetches of future instructions.
There is therefore a need for cache pre-fetching systems that can distinguish between requests for speculative instruction pre-fetches and requests for "mainline" cache misses of needed instructions and assign a higher priority to servicing the cache misses.